A 64-bit comparator is built in a 4-way merge architecture to reduce the number of logic stages. Conventional ways of 4-way merge for a comparator are based on equations: EQU EQ(i)=A(i)B(i)+A.sub.-- B(i)B.sub.-- B(i) EQU GT(i)=A(i)B.sub.-- B(i) EQU LT(i)=A_B(i)B(i) EQU EQ4(i)=EQ(i)EQ(i+1)EQ(i+2)EQ(i+3) EQU GT4(i)=GT(i)+EQ(i)GT(i+1)+EQ(i)EQ(i+1)GT(i+2)+EQ(i)EQ(i+1)EQ(i+2)GT(i+3) EQU LT4(i)=LT(i)+EQ(i)LT(i+1)+EQ(i)EQ(i+1)LT(i+2)+EQ(i)EQ(i+1)EQ(i+2)LT(i+3)
where A, B, A_B, and B_B are true and complemented inputs, EQ stands for EQuivalent, LT stands for Less Than, and GT stands for Greater Than. The above equations involve a 4-way AND, and the total number of logic stages is 4 assuming that the maximum number of transistors allowed on an N stack is 4, which is usually the case.
Such a comparator is often utilized in execution units in a microprocessor or a microcontroller. Chip designers are always searching for new designs that offer faster computation times to thereby increase the throughput of the processor. If a particular circuit or macro can be made faster, then it is often possible to increase the throughput in other circuits or macros. Therefore, what is desired is a faster 64-bit comparator.